The present invention relates to a lateral double diffusion insulated gate field effect transistor (hereinafter referred to as LDMOS) and a semiconductor integrated circuit device including the LDMOS.
In a semiconductor integrated circuit including mixed Bipolar-CMOS-DMOS Circuitry (hereinafter referred to as BiCDMOS), the DMOS Circuitry is mainly used for an output driver circuit where a large current on an ampere level flows. That is, with respect to the characteristics of the DMOS, higher driving performance is required as compared with other elements. When a complementary inverter is especially used as an output circuit, DMOS transistors having two different conductivity types including an N-channel and P-channel type and a having high driving performance are required. Integration of two DMOS transistors of different conductivity types on the same semiconductor substrate is generally realized by adopting a device separation process with a pn junction using an epitaxial layer.
FIG. 2 is a schematic sectional view of a conventional example in which an N-channel LDMOS and a P-channel LDMOS are formed on the same substrate at the same time.
As shown in the drawing, an N-type epitaxial layer 2 is generally formed on a P-type semiconductor substrate 1, and an element is formed in the N-type epitaxial layer 2. Reference numeral 101 denotes an N-channel LDMOS transistor. A P-type low concentration diffusion region 5 is formed by thermal diffusion in a region including an N-type source region 4, and is used as a body region of the LDMOS, so that the MOS transistor having a channel length consisting of a difference in the diffusion amount between the source region 4 below the gate electrode 10 and the P-type low concentration 5 region in a lateral direction is obtained. The outer circumference of the N-channel LDMOS is surrounded by a P-type well layer 11 and a P-type buried layer 12 as separation layers. In this case, the P-type well layer 11 is diffused to such a depth that it reaches the P-type buried layer 12.
Reference numeral 102 denotes a P-channel LDMOS transistor. A P-type well layer 11 is formed, and an element is formed therein. In this case, contrary to the N-channel LDMOS, an N-type low concentration diffusion region 8 is formed by thermal diffusion in a region including a P-type source region 7, and is used as a body region of the LDMOS. Thus, there is formed a MOS transistor having a channel length consisting of a difference in the amount of diffusion between the source region 7 below a gate electrode 10 and the N-type low concentration region 8 in the lateral direction. In case of the P-channel LDMOS, though it depends on a process condition or a desired performance of an element, in order to prevent a decrease in a withstand voltage in the vertical direction and the lateral direction and to prevent a leakage caused by a parasitic element, the circumference and the bottom of the element are surrounded, in this case, by an N-type sinker 14 and an N-type buried layer 13.
The gate electrode 10 is made of polycrystal silicon in any of the foregoing elements, and impurity implantation of the low concentration diffusion region for forming the source region and the body region is carried out by an ion implantation method using the gate electrode as a mask and in a self-aligning manner as shown in FIG. 3. In this process, a photoresist mask layer 18 is used to cover a portion including half of the gate electrode for the purpose of masking the substrate so that an impurity is not implanted in the drain region. That is, in order to prevent the end of the photoresist on the gate electrode from overlapping with any of the source and drain regions, it is preferably set so that the length from the source region end of the gate electrode to the end of the drain is sufficiently large, and the end of the photoresist is positioned at the center thereof. When the process fluctuation of the photoresist and the gate electrode upon patterning is taken into consideration, the minimum value of the length of the gate electrode is around 1.8 .mu.m.
With respect to the drain region, especially in the case where the source-drain withstand voltage is as low as 15 V or less, the drain region is also formed together with the source region in a self-aligning manner using the gate electrode as a mask. By the foregoing steps, in the N-channel LDMOS, a portion below a gate oxide film is formed of two regions consisting of the body region in which the channel is formed and an epitaxial region that becomes a low concentration drain region. A high concentration source region and a high concentration drain region are arranged on the body region side and the epitaxial region side at left and right with the gate electrode as the center, respectively. In case of the P-channel LDMOS, the foregoing region that becomes the low concentration drain region becomes the P-type well layer as shown in FIG. 2.
In the case where high driving performance is an object of the LBMOS transistor, it is desirable for the region that becomes the low concentration drain region below the gate electrode to be as short as the required source-drain withstand voltage can allow. This is because the portion becomes a drain parasitic resistance during transistor operation, and lowers a driving current under non-saturation conditions in the transistor operation. In order to shorten the region of the low concentration drain, it is preferable that the length between the source end of the gate electrode and the drain end is made short. However, when the length is made short, the source-drain withstand voltage is also lowered. Thus, it is necessary to set the length short within a range where a required withstand voltage is satisfied.
However, the conventional method has a problem to be solved as described below.
In a low withstand voltage LDMOS, for the purpose of increasing a driving current, when the length of the gate electrode is shortened to lower the drain parasitic resistance, even if there is allowance in the source-drain withstand voltage, the length can not be made 1.8 .mu.m or less, as described above, due to the restriction caused by process fluctuation during the masking step of forming the body of the LDMOS.
Therefore, in order to solve such a problem inherent in the prior art, an object of the present invention is to increase a driving current without being influenced by process fluctuation at the time of a masking step of forming a body of an LDMOS.